The present invention relates to a semiconductor device and a manufacturing method thereof, and a mounting method of a semiconductor device, and the invention can be preferably applied to a semiconductor device including thick uppermost layer wiring containing, for example, Cu, and a manufacturing method thereof, and a mounting method of a semiconductor device.
In recent years, there is a demand for making one semiconductor chip to be compatible with various mounting configurations. For example, when external terminals arranged at small pitches for wire bonding are converted into those arranged at relatively large pitches for bump electrodes, such as WPP, thick rewiring (rewiring layer, uppermost layer wiring) containing Cu is used over the top surface of a semiconductor chip.
This rewiring layer is also used in other applications besides the aforementioned one in which the pitches of external terminals are converted, and, for example, in Japanese Unexamined Patent Application Publication No. 2007-73611 (Patent Document 1), a technique is disclosed, in which passive elements and wiring coupled thereto are formed over a semiconductor wafer (substrate) by using rewiring. Specifically, a three-layer insulating film including a silicon oxide film, a silicon nitride film, and a polyimide resin film, is formed so as to cover lower layer wiring containing aluminum (Al) that is formed over a substrate. The lower layer wiring has a pad part at the bottom of an opening formed in the three-layer insulating film, and one end of the rewiring containing Cu is coupled to the pad part, while the other end extends over the three-layer insulating film to be coupled to a bump electrode. In order to reduce the stress applied to the bump electrode, the thickness of the polyimide film, formed over a laminated structure including the silicon oxide film and the silicon nitride film, is relatively larger than that of the laminated structure.
Also, in Japanese Unexamined Patent Application Publication No. 1998-92817 (Patent Document 2), it is disclosed that an embedded insulating film having a low dielectric constant and a passivation film having a high dielectric constant and high moisture absorption resistance are sequentially deposited and a surface protective film for the wiring is formed by a composite film of the above two films. It is also disclosed that: a TEOS film deposited by a plasma CVD method is used as the embedded insulating film having a low dielectric constant and a silicon nitride film deposited by a plasma CVD method is used as the passivation film; and the TEOS film is flattened by performing CMP processing before the deposition of the silicon nitride film. In Patent Document 2, it is described that: in a passivation film, it is not necessary to take into consideration poor coverage of a stepped portion, occurrence of a pinhole or a crack, an increase in local stress, or the like; and hence the thickness of the passivation film can be set to a requisite minimum. That is, the flattening of the TEOS film by CMP processing is performed to make the thickness of the passivation film formed thereover to be small.
The present inventors are studying how to improve the operation speed of a semiconductor device by using a rewiring layer as wiring. According to the study by the inventors, it has been revealed that a high-density arrangement of a rewiring layer is difficult in a structure in which a polyimide resin film is provided under rewiring, as described in Patent Document 1. It has also been revealed that, if a structure in which a polyimide resin film, is simply omitted is adopted, a crack is generated in an insulating film under a rewiring layer, and hence the reliability of a semiconductor device is decreased in terms of moisture resistance, etc.
Other problems and new features will become clear from the description and accompanying drawings of the present specification.
A semiconductor device according to an embodiment includes: first wiring formed over a semiconductor substrate via a first insulating film; a second insulating film that includes an inorganic film covering the first wiring and that has a flat upper surface on which CMP processing has been performed; a third insulating film that is formed over the second insulating film and includes an inorganic film having moisture resistance higher than that of the second insulating film; and second wiring formed over the third insulating film. The thickness of the second wiring is 10 times or more larger than that of the first wiring, and the second wiring is located over the third insulating film without an organic insulating film being interposed between itself and the third insulating film.
According to the embodiment, the reliability of a semiconductor device can be improved.